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W536020K/030k/060k/090k/120k voice/melody/lcd controller (viewtalk tm series) publication release date: may 21, 2003 - 1 - revision a3 table of contents- 1. general des cription ......................................................................................................... 2 2. features ....................................................................................................................... .......... 3 3. block di agram .................................................................................................................. .... 5 4. pad descri ption ................................................................................................................... 6 5. electrical chara cteristics ........................................................................................... 9 5.1 absolute maxi mum rati ngs ............................................................................................... 9 5.2 dc characte ristics ............................................................................................................. 9 5.3 ac characte ristics ........................................................................................................... 11 6. typical application circui ts ........................................................................................ 14 6.1 sub clock with rc m ode ................................................................................................. 14 6.2 sub clock with crystal mode ........................................................................................... 15 7. revision history ............................................................................................................... .16
W536020K/030k/060k/090k/120k - 2 - 1. general description the w536xxxk, a member of viewtalk tm family, is a high-performance 4-bit micro-controller (uc) with built-in speech unit, melody unit and 40seg * 8 com lcd driver unit which includes internal regulator, pump circuit and dedicated one page lcd ram. the 4-bit uc core contains dual clock source, 4-bit alu, two 8-bit timers, one 14 bits divider, maximum 24 pads for input or output, 8 interrupt sources and 8-level nesting for subroutine/ interrupt applications. speech unit, integrated as a single chip with maximum 128 seconds (based on 6.4k sample rate with 5 bits mdpcm), is capable of expanding to 512 seconds speech addressed by external memory w55xxx with serial bus interface. it can be implemented with winbond power speech usi ng mdpcm algorithm. melody unit provides dual tone output and can store up to 1k notes. power r eduction mode is also built in to minimize power dissipation. it is ideal for games, educational to ys, remote controllers, watches, clocks and other application products which incorpor ate both lcd display and speech. body W536020K w536030k w536060k w536090k w536120k voice 20 sec 30 sec 60 sec 90 sec 120 sec i/o pad 4i/o,8i (ra/rc/rd) 4i/o, 8i (ra/rc/rd) 8io, 8i (ra/rb/rc/rd) 8i/o, 8i, 8o (ra/rb/rc/rd/re/ rf) 8i/o, 8i, 8o (ra/rb/rc/rd/ re/rf) wdt disable/enable (mask option) y y y y y sub-clock rc/xtal mode (mask option) y y y y y rd port shared as serial bus (mask option) y(1) y(1) n n n (2) tri-state serial bus (mask option) (3) y y n y y cascaded voice rom through serial bus (2) n y(1) n n y notes: 1. share 3 pads of rd port (rd1/clk, rd2/data and rd3/addr) 2. dedicate serial bus 3 pads (clk, data and addr) to interface with w55 xxx. cascaded voice rom can help to expand voice up to 512 sec by w55xxx chip. 3. tri-state serial bus mask option can float serial bus while voice playing is no active. let this mask option is disabled to get minimum power consumption in general.
W536020K/030k/060k/090k/120k publication release date: may 21, 2003 - 3 - revision a3 2. features ? operating voltage: 2.4 volt ~ 5.5 volt ? watch dog disabled/enabled by mask option ? dual clock operating system ? main clock with ring/crystal (400 khz to 4 mhz) ? sub-clock with 32.768 khz rc/crystal by mask option ? memory ? program rom (p-rom): 16k 20 (rom bank0) ? data ram (w-ram): 1k 4 bit (ram bank 0 is 512 nibbles from 0: 000~0: 1ff and 0: 380~0:3ff are mapped to specia register. ram bank f is 512 nibbles from f: 200~f: 3ff either data ram or dedicated to script kernel) ? lcd ram (l-ram): 80 4 bit (ram bank1 from 200~24f) ? maximum 24 input/output pads ? ports for input only: 8 pads (rc, rd port; rd1~3 can share as serial bus for external memory w55xxx interface @w5360020/30k) ? ports for output only: 8 pads (re & rf port; w536090k/120k available only) ? ports for input/output: 8 pads (ra and rb port; rb port is available for w536060/090k/ 120k only) ? power-down mode ? hold mode (except for 32khz oscillator) ? stop mode (including 32khz oscillator and release by rd or rc port) ? eight types of interrupts ? five internal interrupts (divider, timer 0, timer 1, speech, melody) ? three external interrupts (port rc, rd, ra) ? one built-in 14-bit clock frequency divider circuit ? two built-in 8-bit programmable countdown timers ? timer 0: one of two clock sources (fosc/4 or fosc/1024) can be selected ? timer 1: built-in auto-reload function includes in ternal timer, external event counter from rc.0 ? built-in 18/14-bit watchdog timer for system reset. ? powerful instruction sets ? 8-level subroutine (including interrupt) nesting ? lcd driver unit capability ? vlcd higher than (v dd -0.5v) ? built-in voltage regulator to v2 pad ? 40 seg 8 com
W536020K/030k/060k/090k/120k - 4 - 1/8 or 1/4 duty, 1/4 or 1/3 bias, internal pump circuit option by special register com 4~ 7 and seg16~39 can be shared as general input/output by special register either uc rom or voice rom used as lcd picture x speech function provided 640k / 1m/ 2m/ 3m/ 4m bits voice rom for W536020K /030k/060k/090k/120k based on 5 bits mdpcm algorithm voice rom (v-rom) available for uc data or lcd picture data. maximum 8*256 label/interrupt vector (voice section number) available provide two types of speech busy flag to either each go or each trigger maximum up to 16m bits speech address capability interface with external memory w55xxx through serial bus. x melody function provide 1k notes (22bits/ note) dedicated melody rom provide two types of melody busy flag to uc either each note or each song provide 6 kinds of beat, 16 kinds of tempo, and pitch range from g3# to c7 tremolo, triple frequency and 3 kinds of percussion available maximum 31 songs available x can mix speech with melody x multi-engine controller x direct driving speaker /buzzer or dac output x chip on board available
W536020K/030k/060k/090k/120k publ i c at i on rel e ase dat e : may 21, 2003 - 5 - revi si on a3 3. block diagram xin x o u t x 32i x32o lcd dri v e r pc st a c k (8 lev el s ) tim e r 0 tim i n g ge n e r a t o r se g0~ 3 9 v3,v5, v 6 tim e r 1 wat c h dog al u acc div i d e rom 16k* 2 0b i t dh1,d h2 com0~7 lc dram 80*4 b i t da ta ra m 1k*4 bi t sp ecial reg i st er hc f he f i e f evf f l a g 1 psr 0 mr 0 pef fla g 0 l px3 pm 0 lp x2 l px0 l px1 po rt r a vlcd pump & reg u lator tone te s t ra0~ 3 vdd res vdd p vs s l px4 v2 po r t rc p o rt rd rc 0 ~ 3 rd 0 ~ 3 l px5 l py0 l py1 sp c m l d du al t one mel ody m l d _pl a y m l d _bus y mdpcm speech spc _ p l a y s p c _bus y pwm 1 / d a c pwm 2 ro s c p a ra lle l to ser i al v ssp vhi inter r upt ,hol d & stop c ontr o l re0~ 3 rf 0~ 3 p o rt rb rb0~ 3 po r t re p o rt rf add r clk dat a ? a ? ? ? ?? ? t ??3 ? a ? ? ? t a ? a? a ? ?
W536020K/030k/060k/090k/120k - 6 - 4. pad description symbol i/o function xin/rxin i input pad for main clock oscillator. it can be connected to crystal when crystal mode is selected (scr0.2 = 1), otherwise connect a resistor to v dd to generate main system clock wh ile ring mode is selected (scr0.2 = 0 and default). oscillator can be enabled or stopped by set scr0.1 to 1 or clear to 0 separately. external capacitor connects to start oscillation and get more accurate clock when crystal mode xout o output pad for oscillator which is connected to another crystal pad when in crystal mode. external capacitor connects to start oscillation when in crystal mode. x32i/rsub1 i 32.768 khz crystal input pad or external resistor node 1 by mask option . external 15~20pf capacitor connects to start oscillation and get more accurate clock when in crystal mode. x32o/rsub2 o 32.768 khz crystal output pad or external resistor node 2 by mask option. external 15~20pf capacitor connects to start oscillation when in crystal mode. ra0 ~ ra3/tone (9) i/o general input/output port specified by pm1 register. if output mode is selected, pm0 register bit 0 can be used to specify cmos/nmos driving capability option. initial state is i nput mode. ra3 may be uses as tone if bit 0 of mr0 special register is set to logic 1. an interrupt source. rb0 ~ rb3 (9) i/o general input/output port specified by pm2 register. if output mode is selected, pm0 register bit 1 can be used to specify cmos/nmos driving capability option. initial state is input mode (w536060k/090k/120k only.) rc0 ~ rc3 i 4-bit schmitter input with internal pull high option specified by pm3 register bit 2. each pad has an independent interrupt capability specified by pefl special register. interrupt and stop mode wake up source. rc0 is also the external event counter source of timer1. rd0 rd1/clk rd2/data rd3/addr (4) i 4-bit schmitter input port with internal pull high option specified by pm3 register bit 3. each pad has an independent interrupt capability specified by pefh special register. interrupt and stop mode wake up source. rd1~3 will be shared as the exter nal memory w55xxx interface pads while rd port shared as serial bus mask option is enabled @W536020K/030k. for W536020K/030k only, "tri-state serial bus" mask option can use to float addr/clk/datd while "rd port shared as serial bus" mask option is enabled. re0~re3 (9) o output port only. pm3 register bit 0 can be used to specify cmos/nmos driving capability option. (w536090k/120k only) rf0~rf3 (9) o output port only. pm3 register bit 1 can be used to specify cmos/nmos driving capability option. (w536090k/120k only)
W536020K/030k/060k/090k/120k publ i c at i on rel e ase dat e : may 21, 2003 - 7 - revi si on a3 pad description, continued s y m b o l i / o f u n c t i o n res i system reset pad, active low with internal pull-high resistor. test i test pad. active high with internal pull low resistor. r o s c i connect resistor to v dd pad to generate speech or melody playing clock source. p w m 1 / d a c o while speech or melody is active, pw m1/dac is speaker direct driving output or dac output controll ed by voice output file. p w m 2 o while speech or melody is active , pwm2 is another speaker direct driving output. addr (5) o external serial memory address write clock for voice extension (w536120k only). clk (5) o external serial memory address read clock for voice extension. (w536120k only). data (5) i/o external serial memory data in /out for voice extension (w536120k only). seg0 seg15 o dedicated lcd segment output pads. seg16/portn.0 ~ seg19/portn.3 o/o lcd segment output pads, and can be shared as general output by register lcdm3 bit 1. default function is segment pad. seg20/portm.0 ~ seg23/portm.3 o/i lcd segment output pads, and can be shared as general input by register lcdm3 bit 0. default f unction is segment pad and pm5.1=0 to inhibit lcd waveform abnormal. seg24/portl.0 ~ seg27/portl.3 o/o lcd segment output pads, and can be shared as general output by register lcdm2 bit 3. default function is segment pad. seg28/portk.0 ~ seg31/portk.3 o/i lcd segment output pads, and can be shared as general input by register lcdm2 bit 2. default f unction is segment pad and pm5.0=0 to inhibit lcd waveform abnormal. seg32/portj . 0 ~ seg35/portj . 3 o/io lcd segment output pads, and can be shared as general input/output by register lcdm2 bit 1. pm4 register is used to select input or output while shared i/o function is active . default function is segment pad and pm4.3 = 0 to inhibit lcd waveform abnormal. seg36/porti.0 ~ seg39/porti.3 o/io lcd segment output pads, and can be shared as general input/output by register lcdm2 bit 0. pm4 register is used to select input or output while shared i/o function is active. default function is segment pad and pm4.2 = 0 to inhibit lcd waveform abnormal.
W536020K/030k/060k/090k/120k - 8 - pad description, continued symbol i/o function com0 com3 o lcd common signal output pads either 1/8 duty or 1/4duty. the lcd frame rate is controlled by lcdm1 register, and default value lcdm1 = 0111b with 64hz frame rate. com4/porto.0 ~ com7/porto.3 o/i lcd common signal output pads, or shar ed as general input by register lcdm3.2 when in 1/4 duty mode. de fault function is common function and pm5.2 = 0 to inhibit lcd waveform abnormal. dh1, dh2 (6) o connection terminal for voltage double capacitor with 0.1uf. the dh2 connects to capacitor positive node and dh1 negative node if polar capacitor is used. vhi i connect to v6 (lcd's vlcd) or v dd which has higher voltage, to make sure there is no any abnormal leakage current appearance. v3 o lcd com/seg output driving vo ltage. need an external 0.1uf capacitor when 1/4 bias. (lcdm0.1 = 1) v5 v6 (6) o lcd com/seg output driving vo ltage. need an external 0.1uf capacitor to every pad terminal. v2 (6) i/o voltage regulator output pad. an exter nal capacitor is a must. output level can be controlled from 0~fh by lcdm4 register. if internal pump is enabled (lcdm3.3 = 0 and default value), lcd operating voltage (vlcd) will be 3*v2 or 4*v2 depending on 1/3 bias or 1/4 bias. a limitation should be noted that vlcd must be higher than (v dd -0.5v) to avoid chip leakage current. while external reference voltage is selected (lcdm3.3 = 1), v2 pad input voltage can not be over 1.5 volt to inhibit chip damage. v ssp (7) i power ground for pwm or dac playing output. v ss (7) i power ground v ddp (7) i power source for pwm or dac playing output. v dd (7) i power source notes: (4) rd1~3 are shared as clk/data/addr to interface with w55xxx @W536020K/030k. (5) @w536120k only (6) 0.1uf is default value, and capacitor value should be larger than 0.1uf if lcd dot size over 0.5mm * 0.5mm. (7) external application circ uit should connect together, pleas e refer to application circuit. to sure chip operation properly, please bond all v dd , v ddp , v ss and v ssp pads and connect v ss and v ssp from chip outside pcb circuit. (8) vhi pad is bonded to v6 or v dd . (9) when working at nmos open drain mode, ex ternal pull high voltage can't bigger than v dd to avoid leakage current.
W536020K/030k/060k/090k/120k publication release date: may 21, 2003 - 9 - revision a3 5. electrical characteristics 5.1 absolute maximum ratings parameter rating unit supply voltage to ground potential -0.3 to +7.0 v applied input/output voltage -0.3 to +7.0 v power dissipation 120 mw ambient operating temperature 0 to +70 c storage temperature -55 to +150 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. 5.2 dc characteristics (v dd ? v ss = 3.0v, no load, fm = 4 mhz with ring mode, fs = 32.768 khz, with xtal mode, t a = 25 c, stn lcd panel on with dot size 0.5mm*0.5mm; unless otherwise specified) parameter sym. conditions min. typ. max. unit op. voltage v dd 2.4 5.5 v op. current i op1 dual clock with crystal - 600 700 a (no load, no voice, no) dual clock with ring type 600 700 melody) sub-clock only, lcd off 40 50 sub-clock only, lcd on 70 90 hold mode current (no load, lcd off) i op2 sub-clock active only 3 5 a hold mode current (no load, lcd on) i op3 sub-clock active only 35 ua stop mode current i op4 lcd auto off 1 a clk/addr output high current io h1 vout = 2.7v -0.8 ma clk/addr output low current io l1 vout = 0.4v 0.8 ma input low voltage v il - v ss - 0.3 v dd input high voltage v ih - 0.7 - 1 v dd port ra, rb, re, rf output low voltage v abl i ol = 2.0 ma - - 0.4 v port ra, rb, re, rf output high voltage v abh i oh = -2.0 ma 2.4 - - v
W536020K/030k/060k/090k/120k - 10 - dc characteristics, continued parameter sym. conditions min. typ. max. unit pull-up resistor r cd port rc, rd 200 300 400 k : share output ri, rj, rl, rn, rp sink current i ol3 v ol = 0.4v -300 ua res pull-up resistor r res - 50 100 200 k : pwm1/2 source current (8) i sph volume option = 00 -20 ma (r load =8 : between pwm1 volume option = 01 -70 and pwm2) volume option = 10 -110 volume option = 11 -135 pwm1/2 sink current (8) i spl volume option = 00 20 ma (r load = 8 : between pwm1 volume option = 01 70 and pwm2) volume option = 10 110 volume option = 11 135 dac output current i dac v dd = 3v, rl = 100ohm -4 -5 -6 ma lcd supply current i lcd no load, all seg. on - 50 - p a com/seg on resistor r on i oh = r 50 p a 5k 10k : v2 pad output voltage v rr depended on lcdm4 0.7 1.45 v v2 pad output deviation (9) v d1 no load r 5 % v2 pad voltage step v r2 lcdm4 increased 1 50 mv v6 pad output voltage (lcd's vlcd depended on v lcd 1/3 bias & no load 2.85 * v2 2.9 * v2 2.95 * v2 v lcdm4 register) (9) 1/4 bias & no load 3.8 * v2 3.85 * v2 3.9 * v2 v2 input voltage v ext lcdm3.3 = 1 1.5 v notes: (8) pwm current deviation will be r 20%. (9) deviation is governed by lcd dot size. mo re larger lcd dot will get larger deviation..
W536020K/030k/060k/090k/120k publ i c at i on rel e ase dat e : may 21, 2003 - 11 - revi si on a3 5.3 ac characteristics (v dd v ss = 3.0v, no load, fm = 4 mhz w i th ring mode, fs = 32.768 khz, w i th xtal mode, t a = 25 q c, stn lcd on w i th dot size 0.5mm*0.5mm; unless otherw i se specified) p a r a m e t e r s y m . c o n d i t i o n s m i n . t y p . max. unit sub-clock frequency f sub crystal type and x32in and x32o with 17pf external cap. 3 2 7 6 8 h z main-clock frequency f m ring type/crystal type 400k - 4m hz chip operation frequency f os c scr0.0 = 1, f sy s = f sub 3 2 7 6 8 h z scr0.0 = 0; f sy s = f main 4 0 0 k - 4 m i n st ruct ion cy cle time t cy c one machine cycle - 4/f osc - s res e t ac tive width t raw fosc = 32.768 khz 1 - - p s interrupt ac tive width t iaw fosc = 32.768 khz 1 - - p s main clock ring frequency f rxin rxin = 680k : 1 m h z ( 1 0 ) rxin = 330k : 2 m rxin = 200k : 3 m rxin = 130k : 4 m sub-clock rc oscillator f rsub r sub = 680k : 3 2 k h z sub-clock oscillation stable time @ cold start f sto p r sub = 680k : 0 . 8 1 s frequency deviation of main-clock f rxin d 2mhz ' f f f(3v) f (2.4v) f(3v ) 1 0 % frequency deviation of main-clock f rxin = 3 mhz ' f f f(3v) f (2.4v) f(3v ) 1 5 % frequency deviation of main-clock f rxin = 4 mhz ' f f f(3v) f (2.4v) f(3v ) 2 0 % rosc frequency f rosc r os c =680k : 3 m h z frequency deviation of f rosc = 3mhz ' f f f(3v) f (2.4v) f(3v ) 7 . 5 % frame frequency f lcd lcdm1 = 0111 b(default) 64 hz notes: ( 10) t he deviation w ill be +20% w h ile v dd drops from 5.5v to 2.4v based on same resistor
W536020K/030k/060k/090k/120k - 12 - 3 i op vs. mai n cl ock rc mode ? ??? ??? ?? ??? ???? ?? ?? freq (mhz) iop (ua ) ? ? o scillatio n f r eq vs. s u b - c l o c k 20 24 28 32 36 40 44 560 620 680 750 820 1k rsub (kohm) f s u b ( k h z ) ? ?
W536020K/030k/060k/090k/120k publ i c at i on rel e ase dat e : may 21, 2003 - 13 - revi si on a3 main freq vs. rxin 0 1 2 3 4 5 6 130 150 160 200 330 680 2k 3k r x in (k o h m ) fmai n (m hz) 2.4v 3v 4.5v 5.5v voi ce operati ng freq. vs. rosc ? ? ? ? ? ? ?? ? ?? ?? rosc (kohm) f r e q ( m h z ) ? ?
W536020K/030k/060k/090k/120k - 14 - 3 6. typical application circuits 6.1 sub clock w i th rc mode 1/4 bias, v lcd = 4.5v, v dd = 2.4~3.6v vd d p v ddp v ddp vd d xi n x32i o x32i n ___ re s pw m1/ d a c clk / rd1 da ta / r d2 a d d r / rd3 w 536xx x k rosc co m 0 ~ 7 se g 0 ~ 3 9 pw m 2 dh 1 dh 2 v6 v5 v2 v3 vss p vs s speak er spea ker r2 r1 r4 c3 r5 q1 80 50 sw i t c h 47 0 c4 r3 c5 c6 b a tte r y 1 2 c2 c1 c13 c12 c1 0 c1 1 c9 vh i v6 vd d (* 3 ) (* 2 ) (* 1 ) (* 4 ) 40 seg * 8 com lcd panel (*4 ) (*5 ) w5 5 m x x v ddp c o m p o n e n t c 1 c 2 ~ c 4 c 5 ~ c 6 c 7 ~ c 8 c9~c13 r 1 r 2 r 3 r 4 value v dd = 3v 4 . 7 u f 0 . 1 u f 100pf - 0 . 1 ~ 1 u f 680k ? ? ? ? ? ? ? - 0 . 1 ~ 1 u f 680k ? ? ? ? ? ? ?
W536020K/030k/060k/090k/120k publ i c at i on rel e ase dat e : may 21, 2003 - 15 - revi si on a3 6.2 sub clock w i th cry s tal mode 1/3 bias, v lcd = 3v , v dd = 3.6~5.4v vddp vdd p vddp vd d xi n x32 i o x32i n ___ res pw m1/ d ac clk/ rd 1 data/ r d2 addr / rd3 vss vssp w 5 3 6 xxxk ro s c co m 0 ~ 3 s e g 0~39 pw m 2 v2 v3 v5 dh2 dh 1 speaker speaker r1 r4 c3 r5 q1 8050 sw i t ch 470 c4 r3 c5 c6 b a tter y 1 2 c2 c1 c12 c1 1 c10 c9 32 k c7 c8 vdd v6 vh i (*3 ) (* 2 ) (*1 ) (*4 ) 40 s e g * 4co m lcd p a nel (*4 ) (* 5 ) w 55m x x vdd p c o m p o n e n t c 1 c 2 ~ c 4 c 5 ~ c 6 c 7 ~ c 8 c 9 ~ c 1 2 r 1 r 2 r 3 r 4 value v dd = 3v 4 . 7 u f 0 . 1 u f 100pf 1 5 ~ 3 0 p f 0 . 1 ~ 1 u f 680k - 680k /1mhz 350k /2mhz 215k /3mhz 150k /4mhz 100 value v dd = 4.5v 4 . 7 u f 0 . 1 u f 100pf 1 5 ~ 3 0 p f 0 . 1 ~ 1 u f 680k - 750k /1mhz 350k /2mhz 225k /3mhz 160k /4mhz 100 notes: 1. c9~c12 depends on lcd panel dot size. 2. option r5 equals to 100 : if high noise immunity is needed. 3. for dac option application. 4. to ensure that three batteries function w e ll in w536f20 demo board. c 6 should stay close to 5. pad pwm/pwm2 at its best. under the mask rom version, c 5 and c 6 can be skipped. 5. sure chip operation properly , please bond all v ddp , v dd , v ssp and v ss ; and connect v ssp pad to v ss from external pcb circuit.
W536020K/030k/060k/090k/120k - 16 - 3 7. revision history v e r s i o n d a t e writ e r descript i o n a1 sep. 18, 2000 jimmy chen a2 nov. 24, 2000 jimmy chen application circuit modify a3 may 21, 2003 jimmy chen application circuit modify headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5665577 http://www.winbond.com.tw/ taipei office tel: 886-2-8177-7168 fax: 886-2-8751-3579 winbond electronics corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 winbond electronics (h.k.) ltd. no. 378 kwun tong rd., kowloon, hong kong fax: 852-27552064 unit 9-15, 22f, millennium city, tel: 852-27513100 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. winbond electronics (shanghai) ltd. 200336 china fax: 86-21-62365998 27f, 2299 yan an w. rd. shanghai, tel: 86-21-62365999 winbond electronics corporation japan shinyokohama kohoku-ku, yokohama, 222-0033 fax: 81-45-4781800 7f daini-ueno bldg, 3-7-18 tel: 81-45-4781881 9f, no.480, rueiguang rd., neihu district, taipei, 114, taiwan, r.o.c. inform at i on cont ai ned i n t h i s publ i cat i on regardi ng devi ce appl i cat i ons and t h e l i k e i s i n t e nded for suggest i on only and m a y be superseded updates. no representation or warranty is given and no liability is assum e d by w i nbond electronics corp. with respect to the accuracy or use of such inform ation, or infringem e nt of patents or ot her i n t e l l ect ual propert y .

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